1. Field of the Invention
This invention relates to a semiconductor device with a MOS structure and a manufacturing method thereof.
2. Description of the Related Art
The miniaturization of semiconductor devices having a MOS structure, particularly a CMOS structure, has been in progress to meet the demands for higher operation speed and higher performance. This makes it necessary to form not only the low-concentration shallow diffused regions of the source and drain regions in a semiconductor substrate but also the high-concentration diffused regions after the formation of the low-concentration regions so that the high-concentration diffused regions may be of less deep. Making a high-concentration diffused layer less deep, however, causes junction leakage currents due to a silicide layer formed on the high-concentration diffused layer, which also causes a power consumption problem.
To reduce the power consumption, the approach of forming a monocrystalline silicon layer on only the source and drain diffused regions, or on these diffused layers and the gate electrode to make the high-concentration diffused layer less deep has been proposed. With this approach, junction leakage currents resulting from the silicide layer can be suppressed. The structure where monocrystalline silicon is selectively formed on only the diffused layers or on the diffused layers and the gate electrode is called an elevated source-drain (or simply referred to as ESD) structure.
In an example of the process of forming the ESD structure, a gate sidewall insulating film is formed after the formation of a low-concentration diffused layer and silicon monocrystalline growth is performed using hydrogen, dichlorosilane, and hydrogen chloride as gas sources. Then, high-concentration diffused layers are formed from above the monocrystalline silicon layer, thereby producing a MOS device with an ESD structure, for example, a CMOS device. Silicon monocrystalline growth may also be performed after the formation of the high-concentration diffused layers.
In the approach of growing silicon in the conventional ESD-structure CMOS device, there are generally two processes. In a first process, epitaxial silicon growth is performed, with polysilicon (polycrystalline silicon) constituting a gate electrode being exposed. In a second process, epitaxial silicon growth is performed, with polycrystalline silicon constituting a gate electrode not being exposed. Each process, however, has the problems explained below.
FIG. 9 shows an example of the COMS structure formed in the first process.
As shown in FIG. 9, a plurality of well regions 2 are formed at the surface of a silicon substrate 1. The well regions 2 are so formed that they overlap partially with each other. An element isolation insulating film 3 constituting an element isolation region is formed to a specific depth from the surface of the silicon substrate 1 in the overlapping part. In the region on the silicon substrate 1 and excluding the element isolation insulating film 3, that is, in the active region or element forming region, a gate electrode 5 is selectively formed via a gate insulating film 4. On the sidewall of the gate electrode 5, a gate sidewall insulating film 6 is provided.
In the vicinity of the surface of the silicon substrate 1 where neither the gate electrode 5 nor the gate sidewall insulating film 6 is formed, high-concentration diffused layers 7a and 7b are formed so as to sandwich the region directly under the gate electrode 5 between them. These high-concentration diffused layers 7a and 7b extend from the edge of the gate sidewall insulating film 6 to the element isolation insulating film 3. At the silicon substrate 1 surface directly under the gate sidewall insulating film 6 in the region sandwiched between the high-concentration diffused layers 7a and 7b, low-concentration diffused layers 8a and 8b are formed. These low-concentration diffused layers 8a and 8b are formed less deep than the high-concentration diffused layers 7a and 7b. 
Silicon films 10 are formed at the surface of the high-concentration diffused layers 7a and 7b on which neither the gate electrode 5 nor the gate sidewall insulating film 6 has been formed. The silicon films 10 are so formed that they extend from the side of the gate sidewall insulating film 6 to the surfaces of the high-concentration diffused layers 7a and 7b and cover part of the surface of the element isolation insulating film 3.
On the top surface of the gate electrode 5, a silicon film 111 is grown. The upper part of the sidewall of the gate electrode 5 is exposed without being covered with the gate sidewall insulating film 6. From this exposed part, a silicon film 111 is also grown. The silicon film 111 is conductive and functions as part of the gate electrode. Thus, this silicon film 111 and gate electrode 5 form a gate electrode structure.
In the CMOS structure formed by the first process, over-etching times generally have to be provided in etching in the process of forming the sidewall insulating film 6 of the gate, taking into account a margin for process in reactive ion etching (RIE). This makes the upper part, or the shoulder part, of the gate sidewall insulating film 6 being lower than the top surface of the gate electrode 5. When epitaxial silicon growth is performed with the lower shoulder part, a problem arises: the gate electrode 5 assumes the structure having a mushroom shape as shown in FIG. 7, since the top surface of the gate electrode 5 and the upper part of its sidewall are exposed.
The mushroom shape of the part acting as the gate electrode structure has the advantage that, even when the gate electrode 5 is a thin wire, the sheet resistance gets lower in proportion to an increase in the length of the gate electrode. At the same time, however, the following problems arise: the silicon film 111 of the gate electrode structure is liable to be short-circuited with the silicon film 10 on the source-drain regions, and the epitaxial growth of the silicon film 111 on the polycrystalline silicon constituting the gate electrode 5 increases its roughness, making the whole sheet resistance higher.
Furthermore, when the gate sidewall insulating film 6 is thin, another problem arises: even when ion implantation is performed, the mushroom-shaped polycrystalline 111 as shown in FIG. 9 acts as a mask, preventing ions from being implanted in the vicinity of the place just under the gate sidewall insulating film 6.
FIG. 10 shows an example of the CMOS structure formed in the second process. FIG. 10 differs from FIG. 9 in that the silicon oxide film 9 is formed as a cap material on the gate electrode 5. In the second process, to prevent silicon from growing epitaxially on the gate electrode 5, epitaxial silicon growth is performed, with the cap material 9 remaining on the gate electrode 5. The second process can avoid the problem of the short-circuiting of the gate electrode 5 with the silicon film 10 of the source-drain region as found in the first process.
Since the polycrystalline silicon on the gate electrode 5 does not grow laterally, this prevents a T-shaped gate structure, an advantage of the ESD structure, from being formed.
As described above, in the conventional ESD structure manufacturing processes, it is difficult to solve not only an ion implantation problem but also the problem of the short-circuiting of the gate electrode structure with the source region or drain region, while realizing a T-shaped gate structure.
Furthermore, in the process of manufacturing a CMOS with the ESD structure, a junction leakage current problem arises, which will be explained below. FIGS. 9A and 9B are sectional views of a MOSFET structure constituting a CMOS to help explain the junction leakage current problem.
Attention should be given to silicon epitaxial growth in the edge region of the element isolation insulating film 3 to realize the suppression of junction leakage currents, so as to realize an advantage of the ESD structure. Specifically, it is desirable that the epitaxially grown silicon film 10 should run onto the element isolation insulating film to some extent (20 nm to 50 nm).
When an isolation band width of the element isolation insulating film 3 gets smaller as a result of further miniaturization, the element forming regions isolated by the element isolation insulating film 3 are liable to be short-circuited and incapable of operating as a device.
Furthermore, it is difficult to control the process of causing the silicon film 10 to run onto the element isolation insulating film 3 about 20 nm to 50 nm, while keeping selectivity. For this reason, it is often that the silicon hardly runs onto the silicon film 10 as shown in FIG. 11A. The same problem arises in the cases of FIGS. 9 and 10.
For instance, when a silicide film 131 is formed on the basis of the silicon film 10 from the structure of FIG. 11A, a silicide reaction might occur at also the sidewall of the epitaxial silicon film 10 in the edge region of the element isolation insulating film 3. For this reason, the silicide film 131 might be formed to a deep position from the surface of the substrate 1 in the edge region of the element isolation insulating film 3 as shown in FIG. 11B. This causes junction leakage currents to flow significantly. That is, this causes a problem in which a merit of using the ESD structure does not produce much effect in the edge region of the element isolation insulating film 3.
As described above, in the process of manufacturing CMOS devices with the conventional ESD structure, it is difficult to realize such a structure as avoids not only an ion implantation problem but also the problem of the short-circuiting of the gate with the source region or drain region, while realizing a T-shaped gate structure.
It is, accordingly, an object of the present invention to provide a semiconductor device with a T-shaped gate structure and a manufacturing method thereof.
Another object of the present invention is to provide a semiconductor device with a silicide film whose shape is highly controllable and a manufacturing method thereof.